FIR Filter design using Urdhva Triyagbhyam based on Truncated Wallace and Dadda Multiplier as Basic Multiplication Unit

Author:

Neelima K1,Padma C.2,Nalini C.2,Balaji M1

Affiliation:

1. School of Engineering, Mohan Babu University,Department of ECE,Tirupati

2. Sri Venkateswara College of Engineering,Department of ECE,Tirupati

Publisher

IEEE

Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. High Speed Single Precision 64-Tap FIR Filter Using Urdhva Tiryagbhyam Sutra;2024 IEEE Students Conference on Engineering and Systems (SCES);2024-06-21

2. Compressor based Approximate Multipliers for Neural Network Accelerators;2024 International Conference on Advancements in Power, Communication and Intelligent Systems (APCI);2024-06-21

3. Design and Evaluation of 32-Bit N-Tap FIR Filter for Audio Processing Applications;2024 1st International Conference on Innovative Sustainable Technologies for Energy, Mechatronics, and Smart Systems (ISTEMS);2024-04-26

4. RNS based FIR filter design with memory less distributed arithmetic filtering for high speed and low power applications;AIP Conference Proceedings;2024

5. A Hybrid Approach to Optimized n-bit Multiplier Design on FPGA Leveraging Recursive-Wallace Tree with AI Centric Enhancements for FIR Filters and Neural Network Inference;2023 International Conference on Next Generation Electronics (NEleX);2023-12-14

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