Modeling of MOS scaling with emphasis on gate tunneling and source/drain resistance
Author:
Publisher
Elsevier BV
Subject
Electrical and Electronic Engineering,Condensed Matter Physics,General Materials Science
Reference15 articles.
1. CMOS scaling into nanometer regime;Taur;IEEE Proc.,1997
2. Source/drain extension scaling for 0.1 μm and below channel length MOSFETs, IEEE Symposium on VLSI Technology Digest;Thompson,1998
3. Estimating oxide thickness of tunnel oxides down to 1.4 nm using conventional capacitance-voltage measurements on MOS capacitors;Henson;IEEE Electron Device Lett.,1999
4. Practical accuracy analysis of some existing effective channel length and series resistance extraction methods for MOSFETs;Biesemans;IEEE Trans. Electron Devices,1998
5. MOS C–V characterization of ultra-thin gate oxide thickness (1.3–1.8 nm);Choi;IEEE Electron Device Lett.,1999
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