Circuits and Simulation of Quaternary SRAM Using Quantum Dot Channel Field Effect Transistors (QDC-FETs)

Abstract

This paper presents the design and simulation of static random access memory (SRAM) using Quantum Dot Channel Field-Effect Transistors (QDC-FETs). A QDC-FET consist of two quantum dots (3 nm to 4 nm) forming n-channel between the source and drain Quantum Dot Channel (QDC) on a p-Si substrate regions. The quantum dot channel enables higher-mobility transport on very low-mobility substrates. The structure of a quantum dot channel QDC-FET that has shown four-state characteristics of charge carriers from one channel to other channel of the device. It shows that four states can be obtained in an inverter made of four-state QDC-FETs. The four stats QDC-FETs is suitable for quaternary logic application with less complex and more area efficient than existing quaternary logic circuits. The device with four-state has been modeled using Berkeley Short-channel IGFET Model (BSIM) and Analog Behavioral Model (ABM), the model is suitable for transient analysis at circuit level. This model is optimized for a quaternary inverter logic and used to replace a conventional CMOS SRAM.