A New Current Profile Determination Methodology Incorporating Gating Logic to Minimize the Noise of CPU Chip by 40%

Abstract

The present methodology of clock distribution inside high-performance central processing unit chip offers current to ramp linearly or exponentially when the chip comes out of sleep mode to active mode or when the clock starts driving a chip to operate. This linear current ramp leads to power and ground noise due to [Formula: see text]d[Formula: see text]/d[Formula: see text]. In this paper, we have shown that for a given power delivery network (PDN), it is possible to generate a current profile (current versus time), by controlling the current on all the complementary metal oxide semiconductor gates of the clock generation circuits. In our methodology, the time for the chip to reach the maximum saturation current is same when compared with the present linear current ramp methodology. We have also developed a new “optimizer program” to show the existence of a unique single current profile solution, which is different from the present methodology. The proposed method requires understanding of how the minimum value of the power supply voltage (supposed to be always 1[Formula: see text]V for the device) gets changed, when various gates in a clock tree are turned ON at different times ([Formula: see text], parameters of the problem) with different values of current ([Formula: see text], other parameters of the problem). Basically, an ensemble of “[Formula: see text]” number of transistors will be turned ON at time [Formula: see text] while it will pump the total current [Formula: see text]. This understanding generates the derivative function of the minimum noise point with respect to these said parameters, which in turn generates a new set of parameters to optimize the noise point. We have found that this optimizer program works and also converges for the generation of minimum power and ground noise, which is 40% lesser than the conventional approach.