A Novel Gating Approach to Alleviate Power and Ground Noise in Silicon Chips

Abstract

As the performing ability of a silicon chip relies on the power supply voltage, it must be configured using genuine power and ground bond pads for mitigating power and ground noise (PGN), which is directly boosted by the increasing peaks of instantaneous current [Formula: see text] and current ramp [Formula: see text]. To address the same, a novel and compact clock gating (CG) scheme is unveiled in this paper to effectively control the peak of [Formula: see text] and [Formula: see text], thereby subduing PGN. The new CG arrangement is simulated for 90[Formula: see text]nm Predictive Technology Model (PTM90), where it is observed that the scheme reduces 88.80% of [Formula: see text] and 84.19% of average [Formula: see text] in comparison to its no gating counterpart along with a reduction of 80.14% in average power dissipation. These results are found to be more prominent when the proposed circuit configuration is tested in 90[Formula: see text]nm Generic Process Design Kit (GPDK90), proclaiming 88.75% and 84.34% reduction in average [Formula: see text] and average power, respectively, to illustrate its capability of truncating PGN in silicon chips.