A SYSTEMATIC APPROACH TO DESIGN BOOLEAN FUNCTIONS USING CNFETS AND AN ARRAY OF CNFET CAPACITORS

Abstract

A systematic approach for designing Boolean logic gates is presented in this paper. A single array of Carbon nanotube field effect transistor (CNFET) capacitors is utilized as a voltage divider of input signals. Then, a special path, which is consisted of CNFETs with different threshold voltages, connects the proper voltage source to the output node for each voltage level. The main concept is illustrated with the concentration on 3-input functions. However, some other logic gates with higher number of input variables are also proposed within the paper. The sensitivity to diameter variation of CNTs is measured by applying Monte Carlo analysis. It is not needed to use Karnaugh map to simplify expressions and the designs structured with the new method, benefit from low transistor count and a fixed critical path regardless of the number of input variables in comparison with conventional and standard circuitry design methods. Several practical circuits are also deigned, which have the capability of working in low voltages.