A Routing Aggregation for Load Balancing Network-on-Chip

Author:

Zhou Xiaofeng1,Liu Lu1,Zhu Zhangming1,Zhou Duan1

Affiliation:

1. School of Microelectronics, Xidian University, 2 South Taibai Road, Xi'an, Shaanxi, Xi'an 710071, China

Abstract

A routing aggregation (RA) is proposed for load balancing network-on-chip (NoC). The computing nodes with dense traffic and long distance in network are gathered into the same routing node to form a super router. A load balancing routing algorithm for super router is presented to improve the overall performance of NoC. A simulation platform using System C is presented to confirm the feasibility of the proposed design in 2D mesh. The simulation results show that the proposed RA design can reduce the average packet latency and the standard deviation of host link utilization 8% and 33%, respectively compared with the reported routing methods. The area cost and power consumption compared with the reported schemes are 22% and 12% less, respectively.

Publisher

World Scientific Pub Co Pte Lt

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Electrical and Electronic Engineering,Hardware and Architecture

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