A Routing Aggregation for Load Balancing Network-on-Chip
Author:
Affiliation:
1. School of Microelectronics, Xidian University, 2 South Taibai Road, Xi'an, Shaanxi, Xi'an 710071, China
Abstract
Publisher
World Scientific Pub Co Pte Lt
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Electrical and Electronic Engineering,Hardware and Architecture
Link
https://www.worldscientific.com/doi/pdf/10.1142/S0218126615501376
Reference6 articles.
1. A systematic reordering mechanism for on-chip networks using efficient congestion-aware method
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4. Improved Extended XY On-Chip Routing in Diametrical 2D MEsh NOC
5. SRNoC: A novel high performance Shared-Resource routing scheme for Network-on-Chip
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