Approximate Toom–Cook FFT with sparsity aware error tuning in a shared memory architecture

Author:

Ahmed Mohammed Salman,Kalesha Md.,Zahra Andleeb,Abbas ZiaORCID

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference42 articles.

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4. A survey on pipelined FFT hardware architectures;Garrido;J. Signal Process. Syst.,2021

5. S. He, M. Torkelson, Design and implementation of a 1024-point pipeline FFT processor, in: Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No. 98CH36143), 1998, pp. 131–134.

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