SRNoC: A novel high performance Shared-Resource routing scheme for Network-on-Chip

Author:

Shu Hao,Ma Pei-jun,Shi Jiang-yi,Xu Zhao,Yang Lin-an

Publisher

Elsevier BV

Subject

General Engineering

Reference36 articles.

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2. S. Vangal et al., An 80-tile 1.28 TFLOPS network-on-chip in 65nm CMOS, in: Proceedings of the 54th IEEE International Solid-State Circuits Conference, ISSCC 2007, San Francisco, 2007, pp. 95–98.

3. A 48-core IA-32 processor in 45nm CMOS using on-die message-passing and DVFS for performance and power scaling;Howard;IEEE J. Solid-State Circuits,2011

4. Networks on chips: a new SoC paradigm;Benini;IEEE Comput.,2002

5. W.J. Dally, B. Towles, Route packets, not wires: on-chip interconnection networks, in: Proceedings of the 38th Design Automation Conference, 2001, pp. 681–689.

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1. A fuzzy integrated congestion-aware routing algorithm for network on chip;Frontiers of Information Technology & Electronic Engineering;2021-05

2. Dynamic clustering-based routing scheme for 2D-Mesh networks-on-chip;Microelectronics Journal;2018-11

3. Reliable congestion-aware path prediction mechanism in 2D NoCs based on EFuNN;The Journal of Supercomputing;2018-08-02

4. A Routing Aggregation for Load Balancing Network-on-Chip;Journal of Circuits, Systems and Computers;2015-08-27

5. A Novel Critical Path Based Routing Method Based on for NOC;2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security, and 2015 IEEE 12th International Conference on Embedded Software and Systems;2015-08

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