A fuzzy integrated congestion-aware routing algorithm for network on chip
Author:
Publisher
Zhejiang University Press
Subject
Electrical and Electronic Engineering,Computer Networks and Communications,Hardware and Architecture,Signal Processing
Link
https://link.springer.com/content/pdf/10.1631/FITEE.2000069.pdf
Reference30 articles.
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2. Badr HG, Podar S, 1989. An optimal shortest-path routing policy for network computers with regular meshconnected topologies. IEEE Trans Comput, 38(10):1362–1371. https://doi.org/10.1109/12.35831
3. Benini L, de Micheli G, 2002. Networks on chip: a new paradigm for systems on chip design. Design, Automation and Test in Europe Conf and Exhibition, p.418–419. https://doi.org/10.1109/DATE.2002.998307
4. Catania V, Mineo A, Monteleone S, et al., 2016. Cycle-accurate network on chip simulation with Noxim. ACM Trans Model Comput Simul, 27(1):4. https://doi.org/10.1145/2953878
5. Chang EJ, Hsin HK, Lin SY, et al., 2014. Path-congestion-aware adaptive routing with a contention prediction scheme for network-on-chip systems. IEEE Trans Comput Aided Des Integr Circ Syst, 33(1):113–126. https://doi.org/10.1109/TCAD.2013.2282262
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1. Architecture Design of Network on Chip for Reducing Network Delay by Cellular Genetic Algorithm;The proceedings of the 10th Frontier Academic Forum of Electrical Engineering (FAFEE2022);2023
2. Low‐cost regional‐based congestion‐aware routing algorithm for 2D mesh NoC;International Journal of Communication Systems;2022-10
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