Architecture Design of Network on Chip for Reducing Network Delay by Cellular Genetic Algorithm
Author:
Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-99-3404-1_92
Reference13 articles.
1. Zheng, H., Louri, A.: Agile: a learning-enabled power and performance-efficient network-on-chip design. IEEE Trans. Emerg. Top. Comput. 10(1), 223–236 (2022)
2. Jiayi, H., Shilpa, B., Rahul, B.: A voting approach for adaptive network-on-chip power-gating. IEEE Trans. Comput. 70(11), 1962–1975 (2021)
3. Bhaskar, A.V., Venkatesh, T.G.: Performance analysis of network-on-chip in many-core processors. J. Parallel Distrib. Comput. 147, 196–208 (2021)
4. Prasad, B.M.P., Khyamling, P., Basavaraj, T.: An efficient FPGA-based network-on-chip simulation framework utilizing the hard blocks. Circuits Syst. Sig. Process. 39, 5247–5271 (2020)
5. Fahimeh, Y., Raheel, A.: A systematic analysis of power saving techniques for wireless network-on-chip architectures. J. Syst. Architect. 126, 102485 (2022)
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