Improved Read/Write Stability-Based Level Shift 5T Ternary SRAM Cell Design Using Enhanced Gate Diffusion Input BWGCNTFET

Abstract

Nowadays, CNTFET introduced the complexity of SRAM design along with the stability. To overcome these complexities, an enhanced Gate Diffusion Input technique-based Ballistic wrap gate CNTFET (EGDI-BWGCNTFET) technology with ternary static random-access memory (T-SRAM) is proposed in this paper. The aim of the proposed technique is “to give higher stability with less stagnant power consumption, voltage drop and store appropriate read/write value of the SRAM cells”. Here, level shift 5T ternary SRAM cell design using Enhanced Gate Diffusion Input Ballistic wrap gate CNTFET (level shift EGDI-BWGCNTFET 5T-ternary SRAM) is proposed for improving read and write stability. It uses two cross-coupled EGDI-BWGCNTFET ternary inverter, which is used for data storage elements along with one access transistor which is connected with bit line (BL) and word line (WL) with minimum supply voltage resulting in leakage current that is decreased. By this, proposed method reduces delay in the write cycles and read cycles. It provides good read static noise margin (RSNM) and controls precharge voltage. The proposed level shift EGDI-BWGCNTFET 5T-ternary SRAM is done in HSPICE platform. The performance of the proposed level shift EGDI-BWGCNTFET 5T-ternary SRAM design is measured in terms of lower Read Delay 23.25%, 22.94%, 18.38%, 23.97%, lower Write Delay 33.92%, 28.94%, 42.83%, 31.98% compared with the existing methods, such as 8T CNTFET-Ternary SRAM, 24T CNTFET-2Ternary SRAM, 18T CNTFET-Ternary SRAM and 17T CNTFET-Ternary SRAM, respectively.