Author:
Shylashree N.,Hosur Amruta,Praveena N.
Reference7 articles.
1. Srinivasa Raghavan B, Kanchana Bhaaskaran VS. Design of novel multiple valued logic (MVL) circuits. In: 2017 International conference on nextgen electronic technologies: silicon to software (ICNETS2), Chennai, India, pp 371–378
2. Vasundara Patel KS, Gurumurthy KS (2009) Quaternary CMOS combinational logic circuits. In: 2009 international conference on information and multimedia technology, Jeju Island, pp 538–542
3. Shanmugavadivu P, Sugunadevi S, Sukanya B (2016) Study of static noise margin of SRAM based on supply voltage and topologies. IJAR. ISSN Print 2394-7500, ISSN Online 2394-5869
4. Srinivasan P, Bhat AS, Murotiya SL, Gupta A (2015) Design and performance evaluation of a low transistor ternary CNTFET SRAM cell. In: 2015 international conference on electronic design, computer networks & automated verification (EDCAV), Shillong, pp 38–43
5. Moaiyeri MH, Mirzaee RF, Doostaregan A, Navi K, Hashemipour O (2013) A universal method for designing low-power carbon nanotube FET-based multiple valued logic circuits. IET Comput Digital Tech 7(4):167–181
Cited by
3 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献