High Speed Area Optimized Hybrid DA Architecture for 2D-DTCWT

Abstract

In this paper, hybrid architecture for DTCWT computation is designed and implemented on FPGA based on DA algorithm. The distributive arithmetic (DA) algorithm is combined with multiplexer based algorithm to optimize the resource utilization on configurable logic block (CLB). The filter coefficients of DTCWT are quantized, rounded to its nearest integer for DTCWT computation and the loss in rounding and quantization is limited to 0.5[Formula: see text]dB as compared with software implementation. The parallel architecture designed computes row elements simultaneously and pipelined architecture is designed to compute column elements. The proposed architecture is modeled using Verilog and implemented on Xilinx FPGA. The design operates at a maximum frequency of 496[Formula: see text]MHz and consumes power less than 0.2[Formula: see text]W.