Memory Efficient High Speed Systolic Array Architecture Design with Multiplexed Distributed Arithmetic for 2D DTCWT Computation on FPGA
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Published:2019-12-09
Issue:
Volume:
Page:119-132
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ISSN:2232-6979
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Container-title:Informacije MIDEM - Journal of Microelectronics, Electronic Components and Materials
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language:en
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Short-container-title:Informacije MIDEM
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials