Novel DWT/IDWT Architecture for 3D with Nine Stage 2D Parallel Processing using Split Distributed Arithmetic

Abstract

Novel high-speed memory optimized distributed arithmetic (DA)-based architecture is developed and modeled for 3D discrete wavelet transform (DWT). The memory requirement for the proposed architecture is designed to [Formula: see text] pixel dynamic memory space and [Formula: see text] ROM. The proposed 3D-DWT architecture implements 9/7 Daubechies wavelet filters, synthesizes 7127 bytes of memory for temporary storage and uses 758 adders, 36 multiplexers of 16:1 and 36 up counter to realize the 3D-DWT hardware. The 3D-DWT engine is implemented and tested in a Xilinx FPGA Vertex5 XC5VLX155T with high area and power efficiency. The maximum delay in the timing path is 2.676[Formula: see text]ns and the 3D-DWT works at maximum frequency of 381[Formula: see text]MHz clock.