DESIGN AND ANALYSIS OF A NOVEL LOW PDP FULL ADDER CELL-Reference-Cited by-同舟云学术

DESIGN AND ANALYSIS OF A NOVEL LOW PDP FULL ADDER CELL

Published:2011-05 Issue:03 Volume:20 Page:439-445
ISSN:0218-1266
Container-title:Journal of Circuits, Systems and Computers
language:en
Short-container-title:J CIRCUIT SYST COMP

Author:

GHADIRY M. H.¹,A'AIN ABU KHARI²,NADI S. M.³

Affiliation:

1. Islamic Azad University, Arak Branch, Department of Computer Engineering, Arak, Iran

2. Universiti Teknologi Malaysia (UTM), Department of Microelectronic and Computer Engineering (MICE), Johor, Malaysia

3. Islamic Azad University, Ashtian Branch, Department of Computer Engineering, Ashtian, Iran

Abstract

This paper, presents a new full-swing low power high performance full adder circuit in CMOS technology. It benefits from a full swing XOR-XNOR module with no feedback transistors, which decreases delay and power consumption. In addition, high driving capability of COUT module and low PDP design of SUM module contribute to more PDP reduction in cascaded mode. In order to have accurate analysis, the new circuit along with several well-known full adders from literature have been modeled and compared with CADENCE. Comparison consists of power consumption, performance, PDP, and area. Results show that there are improvements in both power consumption and performance. This design trades area with low PDP.

Publisher

World Scientific Pub Co Pte Lt

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Electrical and Electronic Engineering,Hardware and Architecture

Link

https://www.worldscientific.com/doi/pdf/10.1142/S0218126611007323

Reference12 articles.

1. A novel low-power full-adder cell for low voltage

2. High performance low power CMOS dynamic logic for arithmetic circuits

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