A novel low-power full-adder cell for low voltage

Author:

Navi Keivan,Maeen Mehrdad,Foroutan Vahid,Timarchi Somayeh,Kavehei Omid

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference36 articles.

1. Analysis and comparison of the full adder block;Alioto;IEEE Trans. VLSI,2002

2. R. Shalem, E. John, L.K. John, A novel low-power energy recovery full adder cell, in: Proceedings of the Great Lakes Symposium on VLSI, February 1999, pp. 380–383.

3. Low Power Design Methodologies;Pedram,1996

4. Low-power design techniques for high performance CMOS adders;Ko;IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,1995

5. Circuit and architecture trade-offs for high speed multiplication;Song;IEEE J. Solid-Sate Circuits,1991

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