Author:
Navi Keivan,Maeen Mehrdad,Foroutan Vahid,Timarchi Somayeh,Kavehei Omid
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Reference36 articles.
1. Analysis and comparison of the full adder block;Alioto;IEEE Trans. VLSI,2002
2. R. Shalem, E. John, L.K. John, A novel low-power energy recovery full adder cell, in: Proceedings of the Great Lakes Symposium on VLSI, February 1999, pp. 380–383.
3. Low Power Design Methodologies;Pedram,1996
4. Low-power design techniques for high performance CMOS adders;Ko;IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,1995
5. Circuit and architecture trade-offs for high speed multiplication;Song;IEEE J. Solid-Sate Circuits,1991
Cited by
54 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献