Low-Power Capacitor-Splitting DAC with Mixed Switching Schemes for SAR ADCs

Abstract

A low-power capacitor-splitting digital-to-analogue converter (DAC) for successive approximation register (SAR) analogue-to-digital converters (ADCs) is proposed. During the first three bit cycles, with proper switching, there is no average switching power consumption. From the fourth bit cycle, one-side double-level switching scheme or the monotonic one is utilized based on the first two bits. When the first two bits are the same, one-side double-level switching scheme is chosen. Otherwise, the monotonic one is adopted. Thus, the proposed switching method only requires 5.27 CV[Formula: see text] average switching energy, 75.29% less compared to the Sanyal and Sun proposed one.