SAR ADC architecture with 98% reduction in switching energy over conventional scheme
Author:
Affiliation:
1. Electrical and Computer Engineering DepartmentThe University of Texas at Austin2501 Speedway, Stop, 00803AustinTexas78712USA
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/el.2012.3900
Reference5 articles.
1. A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure
2. A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS
3. Merged capacitor switching based SAR ADC with highest switching energy-efficiency
4. Low-energy and area-efficient tri-level switching scheme for SAR ADC
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