Impact of Dimensions and Doping on the Breakdown Voltage of a Trench 4H-SiC Vertical JFET

Abstract

In this paper we study the feasibility of the design/fabrication of a vertical trench 4H-SiC Junction Field Effect Transistor (JFET), assuming realistic constraints of the depth of the P+ implantation. The P+ doping profile is obtained using a Monte Carlo implantation simulation. The calculation used a drift-diffusion approach. The JFET aims to achieve a threshold voltage of-3V. We found that this constraint in concomitance with the proposed structure limits the breakdown voltage to approximately 200V. This is the result of a premature breakdown induced by short channel effects, namely Drain Induced Barrier Lowering (DIBL). However, a negative increase in the gate bias represses this short channel effect and improves the breakdown voltage to roughly 1800V. At this gate bias, the breakdown is induced by reaching the critical field strength of 4H-SiC at the gate P+/N junction, which causes avalanche generation of carriers. In addition, we have calculated the dependence of the threshold voltage on the drift doping and pillar width. This work also shows the vulnerability of the design to random fluctuation in the doping profile.