High-Temperature Reliability of SiC Power MOSFETs

Abstract

We have observed a significant increase in the instability of SiC power MOSFET ID-VGS characteristics following bias stressing at elevated temperature, similar to the effect we previously observed following an ON-state current stress. Devices stressed by elevated temperature alone exhibited very little instability compared with devices stressed with both temperature and applied bias. These results, along with other results in the literature, suggest that this increase in threshold voltage instability at elevated temperature is due to the activation of additional near-interfacial oxide traps related to an O-vacancy defect known as an E′ center. It is important to develop improved processing methods to decrease the number of precursor oxide defect sites, since an increased negative shift can give rise to increased leakage current in the OFF-state and potential device failure if proper precautions are not met to provide an adequate margin for the threshold voltage.