Thermal Analysis of a Face-to-Back Bonded Four-Layer Stacked 3D IC Model

Abstract

Three dimensional integrated circuits (3D ICs) consisted of stacking and vertically interconnecting are an emerging technology with great potential for improving system performance. 3D integration relies on Through Silicon Via (TSV) interconnection and interlayer bonding between the silicon layers. Due to the advantages of higher device density, lesser signal delay, shorter interconnection length and smaller package size, this technology attracts growing attentions. A number of innovative processes contribute to the realization of 3D IC. These include back grinding, coating, cleaning, etching, wafer thinning, filling of high aspect ratio vias with electroplated copper and interlayer bonding, etc. In this work, finite element models for four-layer stacked TSV-based (Through Silicon Via) 3D IC are established based on the heat distribution of working process caused by heat source in device die, in order to investigate the thermal effects and determine the improvements required. The transient temperature fields of 3D IC structures are obtained. The effects of various geometric parameters and thermal properties on the overall temperature have been analyzed. The result indicates that TSV diameter, pitch, BCB thickness and BEOL conductivity play more important roles to the temperature increment and the maximum temperature of no TSV structures is several times of that of TSV-based structures. The copper provides for an effective heat conduction path, and reduces considerably the overall temperature. It is also shown that the heat path from chip to the bottom surface is the main way for the heat dissipation.