1. Thermal cycle reliability of stacked via structures with copper metallization and an organic low-k dielectric;Filippi,2004
2. Comprehensive reliability evaluation of a 90nm CMOS technology with Cu/PECVD low-k BEOL;Edelstein,2004
3. Electrical integrity of state-of-the-art 0.13 mu m SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication;Guarini,2002
4. A wafer-scale 3D IC technology platform using dielectric bonding glues and copper damascene patterned inter-wafer interconnects;Lu,2002