A metastability-immune error-resilient flip-flop for near-threshold variation-tolerant designs
Author:
Affiliation:
1. Institute of VLSI Design, Zhejiang University
2. State Key Laboratory of ASIC and System, Fudan University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/elex/14/11/14_14.20170353/_pdf
Reference13 articles.
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2. [2] W. Shanet al.: “Timing monitoring paths selection for wide voltage IC,” IEICE Electron. Express 13 (2016) 20160095 (DOI: 10.1587/elex.13.20160095).
3. [3] S. Kim and M. Seok: “Variation-tolerant, ultra-low-voltage microprocessor with a low-overhead, within-a-cycle in-situ timing-error detection and correction technique,” IEEE J. Solid-State Circuits 50 (2015) 1478 (DOI: 10.1109/JSSC.2015.2418713).
4. [4] S. Daset al.: “A self-tuning DVS processor using delay-error detection and correction,” IEEE J. Solid-State Circuits 41 (2006) 792 (DOI: 10.1109/JSSC.2006.870912).
5. [5] M. R. Choudhuryet al.: “Time-borrowing circuit designs and hardware prototyping for timing error resilience,” IEEE Trans. Comput. 63 (2014) 497 (DOI: 10.1109/TC.2012.190).
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