Metastability Mitigation and Error Masking of High-Speed Flip-Flop
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Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-16-8721-1_52
Reference15 articles.
1. Sannena G (2018) Low overhead warning flip-flop based on charge sharing for timing slack monitoring. In: IEEE transactions on very large scale integration (VLSI) systems vol 99. pp 1–10 Apr 2018
2. Wang S (2017) A metastability-immune error-resilient flip-flop for near-threshold variation-tolerant designs IEICE Electron Expr 14(11), May 2017
3. Sannena's G (2016) A metastability immune timing error masking flip-flop for dynamic variation tolerance. In: Conference: the 26th edn, May 2016 https://doi.org/10.1145/2902961.2902976
4. Jahinuzzaman SM, Islam R (2010) TSPC-DICE: a single phase clock high performance SEU hardened flip-flop. In: Proceeding of the IEEE international midwest symposium on circuits and systems, pp 73–76
5. Jahinuzzaman SM, Rennie DJ, Sachdev M (2009) Soft error robust impulse and TSPC flip-flops in 90nm CMOS. In: Proceeding of the microsystems and nanoelectronics research conferences. Ottawa, ON, pp 45–48
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