A Metastability Immune Timing Error Masking Flip-Flop for Dynamic Variation Tolerance-Reference-Cited by-同舟云学术

A Metastability Immune Timing Error Masking Flip-Flop for Dynamic Variation Tolerance

Published:2016-05-18 Issue: Volume: Page:
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Container-title:Proceedings of the 26th edition on Great Lakes Symposium on VLSI
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Author:

Sannena Govinda¹,Das Bishnu Prasad¹

Affiliation:

1. Indian Institute of Technology, Roorkee, India

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/2902961.2902976

Reference14 articles.

1. D. Ernst N. S. Kim S. Das S. Pant R. Rao T. Pham C. Ziesler D. Blaauw T. Austin K. Flautner T. Mudge B. Ave and A. Arbor "Razor: a low-power pipeline based on circuit-level timing speculation " in International Symposium on Microarchitecture MICRO-36. 2003 pp. 7--18. D. Ernst N. S. Kim S. Das S. Pant R. Rao T. Pham C. Ziesler D. Blaauw T. Austin K. Flautner T. Mudge B. Ave and A. Arbor "Razor: a low-power pipeline based on circuit-level timing speculation " in International Symposium on Microarchitecture MICRO-36. 2003 pp. 7--18.

2. A Self-Tuning DVS Processor Using Delay-Error Detection and Correction

3. RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance

4. Razor-Lite: A Light-Weight Register for Error Detection by Observing Virtual Supply Rails

5. Adaptive Performance Compensation With In-Situ Timing Error Predictive Sensors for Subthreshold Circuits

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