Metastability immune and area efficient error masking flip-flop for timing error resilient designs-Reference-Cited by-同舟云学术

Metastability immune and area efficient error masking flip-flop for timing error resilient designs

Published:2018-03 Issue: Volume:61 Page:101-113
ISSN:0167-9260
Container-title:Integration
language:en
Short-container-title:Integration

Author:

Sannena Govinda,Das Bishnu Prasad

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference32 articles.

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2. A self-tuning DVS processor using delay-error detection and correction;Das;IEEE J. Solid-State Circuits,2006

3. RazorII: in situ error detection and correction for PVT and SER tolerance;Das;IEEE J. Solid-State Circuits,2009

4. A 45nm resilient microprocessor core for dynamic variation tolerance;Bowman;IEEE J. Solid-State Circuits,2011

5. Razor-lite: a light-weight register for error detection by observing virtual supply rails;Kwon;IEEE J. Solid-State Circuits,2014

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