On Detecting Delay Faults Using Time-to-Digital Converter Embedded in Boundary Scan

Author:

YOTSUYANAGI Hiroyuki1,MAKIMOTO Hiroyuki1,NIMIYA Takanobu1,HASHIZUME Masaki1

Affiliation:

1. The Univ. of Tokushima

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software

Reference16 articles.

1. [1] Y. Sato, S. Hamada, T. Maeda, A. Takatori, Y. Nozuyama, and S. Kajihara, “Invisible delay quality-SDQM model lights up what could not be seen,” Test Conference, International, Paper 47.1, 2005.

2. [2] P.J. Chen, W.L. Hsu, J.C.M. Li, N.H. Tseng, K.Y. Chen, W.P. Changchien, and C.C. Liu, “An accurate timing-aware diagnosis algorithm for multiple small delay defects,” Asian Test Symposium, pp.291-296, 2011.

3. [3] H. Yan and A.D. Singh, “A delay test to differentiate resistive interconnect faults from weak transistor defects,” International Conference on VLSI Design, pp.47-52, 2005.

4. [4] N. Ahmed and M. Tehranipoor, “A novel faster-than-at-speed transition-delay test method considering IR-drop effects,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol.28, no.10, pp.1573-1582, Oct. 2009.

5. [5] B. Kruseman, A.K. Majhi, G. Gronthoud, and S. Eichenberger, “On hazard-free patterns for fine-delay fault testing,” Test Conference, International, pp.213-222, 2004.

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