UnionMixup and max-min-saliency mixup for mixed-type defect recognition of wafer bin maps
Author:
Affiliation:
1. Dept. of Information Management, MinNan University of Science and Technology
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Link
https://www.jstage.jst.go.jp/article/elex/21/10/21_21.20240054/_pdf
Reference33 articles.
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2. [2] C.F. Chien, et al.: “Overall wafer effectiveness (owe): a novel industry standard for semiconductor ecosystem as a whole,” Computers and Industrial Engineering 65 (2013) 117 (DOI: 10.1016/j.cie.2011.11.024).
3. [3] J.C.H. Pan and D.H. Tai: “A new strategy for defect inspection by the virtual inspection in semiconductor wafer fabrication,” Computers and Industrial Engineering 60(2011) 16 (DOI: 10.1016/j.cie.2010.09.008).
4. [4] I. Tirkel: “The efficiency of inspection based on out of control detection in wafer fabrication,” Computers and Industrial Engineering 99 (2016) 458 (DOI: 10.1016/j.cie.2016.05.022).
5. [5] Z. Kang, et al.: “Machine learning applications in production lines: a systematic literature review,” Computers and Industrial Engineering 149 (2020) 106773 (DOI: 10.1016/j.cie.2020.106773).
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