A high-output-swing 64-Gb/s PAM-4 transmitter with a 4-tap hybrid FFE in 28-nm CMOS
Author:
Affiliation:
1. Institute of Microelectronics of the Chinese Academy of Sciences
2. University of Chinese Academy of Sciences
3. Institute of Computing Technology Chinese Academy of Sciences
4. Wuxi Institute of Interconnect Technology
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Link
https://www.jstage.jst.go.jp/article/elex/21/7/21_21.20240104/_pdf
Reference30 articles.
1. [1] K. Zhu, et al.: “A 25Gb/s RX front-end with multi-stage linear equalizer and 3-tap speculative DFE in 65nm CMOS technology,” IEICE Electron. Express 20 (2023) 20220527 (DOI: 10.1587/elex.19.20220527).
2. [2] H. Sun, et al.: “6.25-10Gb/s adaptive CTLE with spectrum balancing and loop-unrolled half-rate DFE in TSMC 0.18µm CMOS,” IEICE Electron. Express 19 (2022) 20220429 (DOI: 10.1587/elex.19.20220429).
3. [3] Y. Kang and J. Song: “A 0.88-pJ/bit 28Gb/s quad-rate 1-FIR 2-IIR decision feedback equalizer with 21dB loss compensation in 65nm CMOS process,” IEICE Electron. Express 18 (2021) 20210253 (DOI: 10.1587/elex.18.20210253).
4. [4] Y. Zhang and X. Yang: “A 36Gb/s wireline receiver with adaptive CTLE and 1-tap speculative DFE in 0.13µm BiCMOS technology,” IEICE Electron. Express 17 (2020) 20200009 (DOI: 10.1587/elex.17.20200009).
5. [5] Z. Guo, et al.: “A 112.5Gb/s ADC-DSP-based PAM-4 long-reach transceiver with >50dB channel loss in 5nm FinFET,” ISSCC Dig. Tech. Papers (2022) 116 (DOI: 10.1109/ISSCC42614.2022.9731650).
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