Adaptive Circuits for the 0.5-V Nanoscale CMOS Era-Reference-Cited by-同舟云学术

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Adaptive Circuits for the 0.5-V Nanoscale CMOS Era

Published:2010 Issue:3 Volume:E93-C Page:216-233
ISSN:0916-8524
Container-title:IEICE Transactions on Electronics
language:en
Short-container-title:IEICE Trans. Electron.

Author:

ITOH Kiyoo¹,YAMAOKA Masanao¹,OSHIMA Takashi¹

Affiliation:

1. Central Research Laboratory, Hitachi, Ltd.

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://www.jstage.jst.go.jp/article/transele/E93.C/3/E93.C_3_216/_pdf

Reference60 articles.

1. [1] K. Itoh, et al., “Low-voltage limitations of memory-rich nano-scale CMOS LSIs,” ESSCIRC Dig., pp.68-75, Sept. 2007.

2. [2] K. Itoh and M. Horiguchi, “Low-voltage scaling limitations for nano-scale CMOS LSIs,” Solid-State Electron., vol.53, no.4, pp.402-410, April 2009.

3. [3] K. Itoh, “Adaptive circuits for the 0.5-V nanoscale CMOS era,” ISSCC Dig., pp.14-20, Feb. 2009.

4. [4] K. Itoh, M. Horiguchi, and H. Tanaka, Ultra-Low Voltage Nano-Scale Memories, Springer, 2007.

5. [5] K. Itoh, VLSI Memory Chip Design, Springer-Verlag, 2001.

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