Low-Voltage Limitations and Challenges of Memory-Rich Nano-Scale CMOS LSIs-Reference-Cited by-同舟云学术

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Low-Voltage Limitations and Challenges of Memory-Rich Nano-Scale CMOS LSIs

Published:2007-12 Issue: Volume: Page:
ISSN:
Container-title:2007 14th IEEE International Conference on Electronics, Circuits and Systems
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Author:

Itoh Kiyoo

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/4456901/4510892/04510907.pdf?arnumber=4510907

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Reducing SRAM Power Using Fine-Grained Wordline Pulse Width Control;Nanometer Variation-Tolerant SRAM;2012-09-26

2. Variation-Tolerant SRAM Write and Read Assist Techniques;Nanometer Variation-Tolerant SRAM;2012-09-26

3. Variability in Nanometer Technologies and Impact on SRAM;Nanometer Variation-Tolerant SRAM;2012-09-26

4. A Low-V_t Small-Offset Gated-Preamplifier for Sub-1-V DRAM Mid-Point Sensing;IEICE Transactions on Electronics;2012

5. Reduction Techniques for Margin Errors of Nanoscale Memories;Integrated Circuits and Systems;2010-11-26

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