A Forward/Reverse Body Bias Generator with Wide Supply-Range down to Threshold Voltage
Author:
Affiliation:
1. Kyoto University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/transele/E98.C/6/E98.C_504/_pdf
Reference13 articles.
1. [1] S. Dighe, S. Vangal, P. Aseron, S. Kumar, T. Jacob, K. Bowman, J. Howard, J. Tschanz, V. Erraguntla, N. Borkar, V. De, and S. Borkar, “Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor,” Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International, pp.174–175, Feb. 2010.
2. [2] F. Tachibana, H. Sato, T. Yamashita, H. Hara, T. Kitahara, S. Nomura, F. Yamane, Y. Tsuboi, K. Seki, S. Matsumoto, Y. Watanabe, and M. Hamada, “A process variation compensation scheme using cell-based forward body-biasing circuits usable for 1.2 V design,” IEEE Custom Integrated Circuits Conference, 2008. CICC 2008, pp.29–32, 2008.
3. [3] R. Teodorescu, J. Nakano, A. Tiwari, and J. Torrellas, “Mitigating parameter variation with dynamic fine-grain body biasing,” Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture, Washington, DC, USA, pp.27–42, 2007.
4. [4] J. W. Tschanz, J. T. Kao, S. G. Narendra, R. Nair, D. A. Antoniadis, A. P. Chandrakasan, and V. De, “Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage,” IEEE J. Solid-State Circuits, vol.37, no.11, pp.1396–1402, Nov. 2002.
5. [5] N. Kamae, A. Tsuchiya, and H. Onodera, “A body bias generator with low supply voltage for within-die variability compensation,” IEICE Trans. Fundamentals, vol.E97-A, no.3, pp.734–740, 2014.
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