A DLL-Based Body Bias Generator with Independent P-Well and N-Well Biasing for Minimum Energy Operation
Author:
Affiliation:
1. Department of Communications and Computer Engineering, Graduate School of Informatics, Kyoto University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/transele/E104.C/10/E104.C_2020CTP0002/_pdf
Reference31 articles.
1. [1] J.W. Tschanz, J.T. Kao, S.G. Narendra, R. Nair, D.A. Antoniadis, A.P. Chandrakasan, and V. De, “Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage,” IEEE Journal of Solid-State Circuits, vol.37, no.11, pp.1396-1402, 2002. 10.1109/jssc.2002.803949
2. [2] S.V. Kumar, C.H. Kim, and S.S. Sapatnekar, “Body bias voltage computations for process and temperature compensation,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.16, no.3, pp.249-262, 2008. 10.1109/tvlsi.2007.912137
3. [3] L. Yan, J. Luo, and N.K. Jha, “Joint dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.24, no.7, pp.1030-1041, 2005. 10.1109/tcad.2005.850895
4. [4] S.M. Martin, K. Flautner, T. Mudge, and D. Blaauw, “Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads,” IEEE/ACM International Conference on Computer Aided Design, 2002, ICCAD 2002, pp.721-725, 2002. 10.1109/iccad.2002.1167611
5. [5] A. Basu, S.-C. Lin, V. Wason, A. Mehrotrat, and K. Banerjee, “Simultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant era,” Proceedings. 41st Design Automation Conference, 2004, pp.884-887, 2004. 10.1145/996566.996801
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