High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer-Reference-Cited by-同舟云学术

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High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer

Published:2009 Issue:6 Volume:E92-C Page:890-893
ISSN:0916-8524
Container-title:IEICE Transactions on Electronics
language:en
Short-container-title:IEICE Trans. Electron.

Author:

LO Yu-Lung¹,YANG Wei-Bin²,CHAO Ting-Sheng³,CHENG Kuo-Hsing⁴

Affiliation:

1. Department of Microelectronics Engineering, National Kaohsiung Marine University

2. Department of Electrical Engineering, Tamkang University

3. Industrial Technology Research Institute (ITRI)

4. Department of Electrical Engineering, National Central University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://www.jstage.jst.go.jp/article/transele/E92.C/6/E92.C_6_890/_pdf

Reference7 articles.

1. High-speed divide-by-4/5 counter for a dual-modulus prescaler

2. A 1.6-GHz dual modulus prescaler using the extended true-single-phase-clock CMOS circuit technique (E-TSPC)

3. A 1.2 GHz CMOS dual-modulus prescaler using new dynamic D-type flip-flops

4. New dynamic flip-flops for high-speed dual-modulus prescaler

5. High-speed CMOS circuit technique

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Low Voltage and Low Power Divide-By-2/3 Counter Design Using Pass Transistor Logic Circuit Technique;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2012-09

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