High-speed divide-by-4/5 counter for a dual-modulus prescaler
Author:
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://digital-library.theiet.org/content/journals/10.1049/el_19971175?crawler=true&mimetype=application/pdf
Reference7 articles.
1. High-speed architecture for a programmable frequency divider and a dual-modulus prescaler
2. High-speed CMOS circuit technique
3. A 700-MHz 24-b pipelined accumulator in 1.2- mu m CMOS for application as a numerically controlled oscillator
4. Speed optimization of edge-triggered CMOS circuits for gigahertz single-phase clocks
5. A 1.2 GHz CMOS dual-modulus prescaler using new dynamic D-type flip-flops
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1. High-Speed CMOS Frequency Dividers with Symmetric In-Phase and Quadrature Waveforms;Journal of Circuits, Systems and Computers;2016-07-22
2. A 37 GHz wide-band programmable divide-by-N frequency divider for millimeter-wave silicon-based phase-locked loop frequency synthesizers;Journal of Zhejiang University SCIENCE C;2014-12
3. High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer;IEICE Transactions on Electronics;2009
4. Dual-modulus 127/128 FOM enhanced prescaler design in 0.35-/spl mu/m CMOS technology;IEEE Journal of Solid-State Circuits;2005-08
5. Dual-Modulus Prescaler Based on Transmission Gates and Pseudo-PMOS Logic;Analog Integrated Circuits and Signal Processing;2005-04
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