New dynamic flip-flops for high-speed dual-modulus prescaler

Author:

Ching-Yuan Yang ,Guang-Kaai Dehng ,June-Ming Hsu ,Shen-Iuan Liu

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 47 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A 4/5 or 8/9 High-Speed Wide Band Programmable Prescaler;2023 3rd Asia-Pacific Conference on Communications Technology and Computer Science (ACCTCS);2023-02

2. Design of Low Power and High-Speed Cmos D Flipflop using Supply Voltage Level (SVL) Methods;International Journal of Innovative Technology and Exploring Engineering;2022-04-30

3. A 0.4-V 0.66-fJ/Cycle Retentive True-Single-Phase-Clock 18T Flip-Flop in 28-nm Fully-Depleted SOI CMOS;IEEE Transactions on Circuits and Systems I: Regular Papers;2018-03

4. A 580- $\mu$ W 2.4-GHz ZigBee Receiver Front End With Transformer Coupling Technique;IEEE Microwave and Wireless Components Letters;2018-02

5. High Speed-Low Power Divide-by-16/17 Dual Modulus Prescaler Using C2MOS;Proceeding of International Conference on Intelligent Communication, Control and Devices;2016-09-18

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