A 1.6-GHz dual modulus prescaler using the extended true-single-phase-clock CMOS circuit technique (E-TSPC)

Author:

Navarro Soares J.,Van Noije W.A.M.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 53 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. An Efficient Architecture Design of High-Speed Dual-Modulus Prescaler for Frequency Synthesizers;2023 International Conference on Consumer Electronics - Taiwan (ICCE-Taiwan);2023-07-17

2. An Extended Range Divider Technique for Multi-Band PLL;Journal of Low Power Electronics and Applications;2023-07-05

3. A 0.35-mW 70-GHz Self-Resonant E-TSPC Frequency Divider With Backgate Adjustment;IEEE Transactions on Microwave Theory and Techniques;2022-04

4. High speed divide by 3/4 prescaler using NMOS like latch block;2021 5th International Conference on Electrical, Electronics, Communication, Computer Technologies and Optimization Techniques (ICEECCOT);2021-12-10

5. Performance Comparison of High-Speed Dual Modulus Prescalers Using Metaheuristic Sizing/Optimization;2020 33rd Symposium on Integrated Circuits and Systems Design (SBCCI);2020-08

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