An Efficient Architecture Design of High-Speed Dual-Modulus Prescaler for Frequency Synthesizers-Reference-Cited by-同舟云学术

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An Efficient Architecture Design of High-Speed Dual-Modulus Prescaler for Frequency Synthesizers

Published:2023-07-17 Issue: Volume: Page:
ISSN:
Container-title:2023 International Conference on Consumer Electronics - Taiwan (ICCE-Taiwan)
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Author:

Arulnambi Devavarshini¹,Syed Khutiza Afrose¹,Kuo Yue-Fang¹,Wu Po-Hsien¹

Affiliation:

1. Yuan Ze University,Dept. of Electrical Engineering,Taoyuan City,Taiwan,32003

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10226627/10226615/10226623.pdf?arnumber=10226623

Reference4 articles.

1. A 5.8-GHz Wideband TSPC Divide-by-16/17 Dual Modulus Prescaler;zhu;IEEE Trans Very Large Scale Integr (VLSI) Syst,2015

2. Design and optimization of the extended true single-phase clock-based prescaler;peng;IEEE Trans Microw Theory Tech,2006

3. A 2 V 1.8 GHz fully integrated CMOS dual-loop frequency synthesizer

4. A 1.6-GHz dual modulus prescaler using the extended true-single-phase-clock CMOS circuit technique (E-TSPC)

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