Investigation of parasitic bipolar transistor in rail-based electrostatic discharge (ESD) protection circuits

Author:

Lai Pengyu12,Li Xianrui1,Wang Hui2,Chen Zhong2

Affiliation:

1. Key Lab. of High-Speed Circuit Design and EMC, Xidian University

2. Department of Electrical Engineering, University of Arkansas

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference33 articles.

1. [1] C. Duvvury: “ESD qualification changes for 45 nm and beyond,” Proc. IEDM (2008) 1 (DOI: 10.1109/IEDM.2008.4796688).

2. [2] A.-Z. Wang, et al.: “On-chip ESD protection design for integrated circuits: An overview for IC designers,” Microelectronics J. 32 (2001) 733 (DOI: 10.1016/S0026-2692(01)00060-X).

3. [3] H. Gossner: “Design for ESD protection at its limits,” VLSI Technol. Symp. Dig. Tech. Papers (2013) T120.

4. [4] S. Voldman: ESD Circuits and Devices (Wiley, New York, 2006).

5. [5] M. P. J. Mergens, et al.: “Analysis of lateral DMOS power devices under ESD stress conditions,” IEEE Trans. Electron Devices 47 (2000) 2128 (DOI: 10.1109/16.877175).

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