On-chip ESD protection design for integrated circuits: an overview for IC designers-Reference-Cited by-同舟云学术

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On-chip ESD protection design for integrated circuits: an overview for IC designers

Published:2001-09 Issue:9 Volume:32 Page:733-747
ISSN:0026-2692
Container-title:Microelectronics Journal
language:en
Short-container-title:Microelectronics Journal

Author:

Wang A.Z,Feng H.G,Gong K,Zhan R.Y,Stine J

Publisher

Elsevier BV

Subject

General Engineering

Reference71 articles.

1. ESD design methodology;Merril;Proc. 15th EOS/ESD Symp.,1993

2. Review of EOS/ESD field failures in military equipment;Green;Proc. 10th EOS/ESD Symp.,1988

3. Modeling of Electrical Overstress in Integrated Circuits;Diaz,1994

4. ESD in Silicon Integrated Circuits;Amerasekera,1995

5. Basic ESD and I/O Design;Dabral,1998

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1. A novel low trigger voltage low leakage SCR for low-voltage ESD protection;Semiconductor Science and Technology;2024-01-12

2. Design and verification of a hybrid electrostatic discharge model for Gate-Controlled silicon controlled rectifier;Solid-State Electronics;2023-11

3. Ultra-Low-Voltage-Triggered Silicon Controlled Rectifier ESD Protection Device for 2.5 V Nano Integrated Circuit;Nanomaterials;2022-11-29

4. The Role of Inorganic Fillers in Electrostatic Discharge Composites;Inorganics;2022-11-25

5. ESD Protection Designs: Topical Overview and Perspective;IEEE Transactions on Device and Materials Reliability;2022-09

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