A Body Bias Generator with Low Supply Voltage for Within-Die Variability Compensation-Reference-Cited by-同舟云学术

A Body Bias Generator with Low Supply Voltage for Within-Die Variability Compensation

Published:2014 Issue:3 Volume:E97.A Page:734-740
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

KAMAE Norihiro¹,TSUCHIYA Akira¹,ONODERA Hidetoshi¹²

Affiliation:

1. Department of Communications and Computer Engineering, Graduate School of Informatics, Kyoto University

2. CREST, JST

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

https://www.jstage.jst.go.jp/article/transfun/E97.A/3/E97.A_734/_pdf

Reference10 articles.

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2. [2] I. Ahsan, N. Zamdmer, O. Glushchenkov, R. Logan, E. Nowak, H. Kimura, J. Zimmerman, G. Berg, J. Herman, E. Maciejewski, A. Chan, A. Azuma, S. Deshpande, B. Dirahoui, G. Freeman, A. Gabor, M. Gribelyuk, S. Huang, M. Kumar, K. Miyamoto, D. Mocuta, A. Mahorowala, E. Leobandung, H. Utomo, and B. Walsh, “RTA-driven intra-die variations in stage delay, and parametric sensitivities for 65nm technology,” Symposium on VLSI Technology, Digest of Technical Papers, pp.170-171, 2006.

3. [3] S. Dighe, S. Vangal, P. Aseron, S. Kumar, T. Jacob, K. Bowman, J. Howard, J. Tschanz, V. Erraguntla, N. Borkar, V. De, and S. Borkar, “Within-die variation-aware dynamic-voltage-frequency-scaling with optimal core allocation and thread hopping for the 80-core TeraFLOPS processor,” IEEE J. Solid-State Circuits, vol.46, no.1, pp.184-193, 2011.

4. [4] M. Meijer, J. de Gyvez, B. Kup, B. van Uden, P. Bastiaansen, M. Lammers, and M. Vertregt, “A forward body bias generator for digital CMOS circuits with supply voltage scaling,” Proc. 2010 IEEE International Symposium on Circuits and Systems (ISCAS), pp.2482-2485, June 2010.

5. [5] M. Sumita, “High resolution body bias techniques for reducing the impacts of leakage current and parasitic bipolar,” ISLPED'05: Proc. 2005 international symposium on Low power electronics and design, pp.203-208, ACM, New York, NY, USA, 2005.

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