Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor

Author:

Dighe S,Vangal S R,Aseron P,Kumar S,Jacob T,Bowman K A,Howard J,Tschanz J,Erraguntla V,Borkar N,De V K,Borkar S

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

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