Author:
Mishra Jitendra Kumar,Upadhyay Bharat Bhushan,Misra Prasanna Kumar,Goswami Manish
Publisher
Springer Science and Business Media LLC
Subject
Applied Mathematics,Signal Processing
Reference26 articles.
1. K.I. Agawa, H. Hara, T. Takayanagi, T. Kuroda, A bitline leakage compensation scheme for low-voltage SRAMs. IEEE J. Solid-State Circuits 36(5), 726–734 (2001)
2. M. Blagojević, M. Cochet, B. Keller, P. Flatresse, A. Vladimirescu, B. Nikolić, A fast, flexible, positive and negative adaptive body-bias generator in 28 nm FDSOI, in 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), Honolulu, HI, pp. 1–2 (2016)
3. B.H. Calhoun, A.P. Chandrakasan, A 256-kb 65-nm sub-threshold SRAM design for ultra-low-voltage operation. IEEE J. Solid-State Circuits 42(3), 680–688 (2007)
4. M.F. Chang, C.F. Chen, T.H. Chang, C.C. Shuai, Y.Y. Wang, Y.J. Chen, H. Yamauchi, A compact-area low-VDD min 6T SRAM with improvement in cell stability, read speed and write margin using a dual-split-control-assist scheme. IEEE J. Solid-State Circuits 52(9), 2498–2514 (2017)
5. L. Chang, D.M. Fried, J. Hergenrother, J.W. Sleight, R.H. Dennard, R.K. Montoye, L. Sekaric, S.J. McNab, A.W. Topol, C.D. Adams, K.W. Guarini, Stable SRAM cell design for the 32 nm node and beyond, in Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005, IEEE, pp. 128–129 (2005)
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