Single-Bit Architecture for Low Power IoT Applications
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Publisher
Springer International Publishing
Link
https://link.springer.com/content/pdf/10.1007/978-3-031-20429-6_23
Reference32 articles.
1. Dounavi, H.-M., Sfikas, Y., Tsiatouhas, Y.: Aging prediction and tolerance for the SRAM memory cell and sense amplifier. J. Electron. Test. 37(1), 65–82 (2021). https://doi.org/10.1007/s10836-021-05932-6
2. Fritsch, A., et al.: 24.1 A 6.2 GHz Single-Ended Current Sense Amplifier (CSA) Based Compileable 8T SRAM in 7nm FinFET Technology. In: 2021 IEEE International Solid-State Circuits Conference (ISSCC), vol. 64. IEEE (2021)
3. Chen, J., et al.: Analysis and optimization strategies toward reliable and high-speed 6T compute SRAM. IEEE Trans. Circ. Syst. I Reg. Papers 68.4, 1520–1531 (2021)
4. Agrawal, R., Tomar, V.K.: Analysis of cache (SRAM) memory for core I™ 7 processor. In: 2018 9th International Conference on Computing, Communication and Networking Technologies (ICCCNT). IEEE (2018)
5. Krishnaraj, R., et al.: Design of a memory array using tail transistor and sleep transistor based 7T SRAM with low short circuit and standby power. In: IOP Conference Series: Materials Science and Engineering, vol. 1084(1). IOP Publishing (2021)
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