An energy efficient full adder cell for low voltage-Reference-Cited by-同舟云学术

An energy efficient full adder cell for low voltage

Published:2009 Issue:9 Volume:6 Page:553-559
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Navi Keivan¹,Maeen Mehrdad²,Hashemipour Omid¹

Affiliation:

1. Faculty of Electrical and Computer Engineering of Shahid Beheshti University

2. Department of Computer Engineering, Science & Research Branch of IAU

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

http://www.jstage.jst.go.jp/article/elex/6/9/6_9_553/_pdf

Reference6 articles.

1. [1] C. H. Chang, J. Gu, and M. Zhang, “A review of 0.18um full adder performances for tree structure arithmetic circuits, ”IEEE Trans. VLSI Syst., vol. 13, no. 6, June 2005.

2. Two new low-power Full Adders based on majority-not gates

3. Ultra high speed Full Adders

4. [4] K. Navi, M. Maeen, V. Foroutan, S. Timarchi, and O. Kavehei, “A novel low power full-adder cell for low voltage, ”To be appeared in Elsevier, Integration, the VLSI Journal.

5. [5] J. T. Kao and A. P. Chandrakasan, “Dual-threshold voltage techniques for low-power digital circuits, ”IEEE JSSC, 35(7): pp. 1009-1018, July 2000.

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