High Performance Wallace Tree Multiplier Using Majority Gate Based Adders

Abstract

Abstract An area efficient high performance Wallace Tree Multiplier using Majority Gate based Adders is presented in this paper. The proposed Wallace tree multiplier is designed using 9T majority function based full adder. Design is implemented in Cadence Virtuoso® using a 180nm technology library. The design and analysis of the proposed design offers reduced delay of 33.12% while compared to the conventional wallace tree multiplier design using 16T full adder. The design also offers reduced transistor count of 208 which is minimal compared to that of the conventional design.