Abstract
In recent years, with the continuous upgrading of the chip manufacturing industry, the requirements of circuit design are not only to complete more and more complex signal conditioning tasks, but also to put forward higher requirements for performance delay and other aspects. This paper designs a 4-bit Absolute-Value Detector circuit and uses half-adder to realize signal conversion. In my circuits, when V dd is 1v, the critical path delay is 63.04 FO4(1V), and the total energy is 186.97 EU(1V). This also provides a solution for circuits that pursue low power consumption and low latency.
Publisher
Darcy & Roy Press Co. Ltd.
Reference10 articles.
1. Science - Computer Science; Researchers' Work from Nanjing University Focuses on Computer Science (A Scalable Virtual Memory System Based On Decentralization for Many-cores)[J]. Computer Technology Journal, 2020,
2. AlBdairi Ahmed Jawad A. et al. Face Recognition Based on Deep Learning and FPGA for Ethnicity Identification[J]. Applied Sciences, 2022, 12(5) : 2605-2605.
3. Mummudi Murasu M et al. High Performance Wallace Tree Multiplier Using Majority Gate Based Adders[J]. IOP Conference Series: Materials Science and Engineering, 2021, 1187(1)
4. Barati Ramin, . High speed low power multipliers based on reversible logic methods[J]. e-Prime - Advances in Electrical Engineering, Electronics and Energy, 2022, 2
5. Renesas Electronics Corporation; Patent Issued for Array-Type Processor Having Delay Adjusting Circuit for Adjusting a Clock Cycle in Accordance with a Critical Path Delay of the Data Path[J]. Information Technology Newsweekly, 2013,
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