An optimal low energy cost 4-bit absolute value detector with 55.5 FO4(1V) based on CMOS process
Reference10 articles.
1. Lin, Xue, et al. “An Improved Logical Effort Model and Framework Applied to Optimal Sizing of Circuits Operating in Multiple Supply Voltage Regimes.” Fifteenth International Symposium on Quality Electronic Design, Mar. 2014.
2. Lubaba, Samiha, et al. “Design of a Two-Bit Magnitude Comparator Based on Pass Transistor, Transmission Gate and Conventional Static CMOS Logic.” 2020 11th International Conference on Computing, Communication and Networking Technologies (ICCCNT), July 2020.
3. Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques
4. Kumar, KVKVL Pavan, et al. "Performance Analysis of Various Full Adders." International Journal of Advanced Science and Technology vol. 29, no. 3, 2020, pp. 591–598.
5. Sahoo, Deepesh, et al. “Study of Different Adders Using Full Swing Gate Diffusion Input.” 2020 5th IEEE International Conference on Recent Advances and Innovations in Engineering (ICRAIE), 1 Dec. 2020.